The finished chip is now ready for packaging and testing.
I don’t have a wire bonder (accepting donations!) so my testing right now is limited to manually probing the wafer with sharp tweezers or using a flip-chip board (difficult to align) to connect it to a curve tracer. The differential amplifier is also tested empirically in-circuit to verify operation.
FET Ids/Vds curve from previous NMOS device
Of course, these curves are far from ideal (some of which is due to extra contact resistance/other factors like that) but I would expect things to get better with proper wire bonding. This may also account for some of the die to die variation. This page will be updated with new IV, FET, and a differential amplifier characteristic curves soon.
Thanks for following my work and feel free to contact me with your thoughts at firstname.lastname@example.org !